Chips & semiconductors · This week (published July 25)
From the Jul 25, 2026 daily brief
AMD's next flagship AI chip, the MI455X, is the first datacenter chip on TSMC's 2nm process; its 3,470 mm² of logic silicon is the most in any single package in the industry, and its 12-stack HBM4 memory totals 432GB against 288GB for Nvidia and Google — all hard leads. But SemiAnalysis rates the GPU's microarchitecture a generation behind Nvidia and converging toward its rival in multiple places (down to native support for Nvidia's 4-bit number format) — silicon area brute-forcing a design gap. Microarchitecture is the chip's internal design itself: it decides how much performance the same silicon can squeeze out. Nvidia, in response, is pushing its next-generation memory pin speeds beyond the official spec to claw back the bandwidth gap (SemiAnalysis, Jul 25). Same source and article as thread 1: the specs have official grounding, the ratings are one firm's judgment.
Just an email address, unsubscribe anytime. This is the only thing we ask of you.
Product leaders from five electronic design automation and AI chip-design tool vendors sai…
OpenAI's enterprise announcement on September 9 recast this model from "the smartest model…
A document signed by CFO Sarah Friar gives the first numbers for Jalapeño, OpenAI's first …
Meta introduced Muse on September 8: it runs on a cloud virtual machine dedicated to each …