Chips & semiconductors · This quarter (event dates 07-16 to 07-19)
From the Aug 16, 2026 daily brief
Advanced packaging is the back-end step that bonds GPU dies to high-bandwidth memory, and through this AI build-out the capacity limit has sat here rather than in front-end wafer fabrication. Three things from mid-to-late July, side by side: TSMC's chairman publicly welcomed a successful packaging offering from his competitor Intel so that it could take some of his own load (see main line item 1); Broadcom and Taiwan's Powertech announced a US$400M joint venture to build a packaging substrate plant in Singapore, with Powertech having developed fan-out panel-level packaging for large dies — a separate technology route using square panels rather than wafer-shaped substrates, not an expansion of the existing mainstream process (Dan Nystedt, 07-16); and UMC, Taiwan's second-largest contract chipmaker, is planning a plant expansion on advanced packaging orders spilling over, silicon interposers among them (Dan Nystedt, 07-19). ⚠️ All three were relayed by the same reporter, so they do not corroborate each other, and most of them give no amounts, no capacity and no timelines. A counter-intuitive reading: orders spilling over to second-tier houses while an alternative technology route enters at the same time is an early signal of a bottleneck easing, not worsening. Read the other way round, it is also the reason the price and margin peak for advanced packaging may land in 2026 rather than later.
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