Product & chips · Aug 31, 2026

On-chip high-speed memory shrinks 25% in area and writes 42% faster.

Chips & semiconductors · This week (published August 30)

From the Aug 31, 2026 daily brief

Georgia Tech and the electronic design software vendor Synopsys published a paper on the 6-transistor SRAM built on a 2-nanometre process. SRAM is the small, fast memory sitting next to the compute units, and one of the largest consumers of area on a chip. The approach stacks it vertically: the access transistors move up into the metal interconnect layers, paired with silicon nanosheets and buried power rails. The cell comes out 25% smaller in area than the high-performance silicon baseline, and sub-array write latency 42.2% lower (Semiconductor Engineering, 08-30; the paper, arXiv 2608.22741, August 2026). Why it is worth keeping: since SRAM is one of the biggest area consumers on a chip, 25% less of it pushes in the direction of that sentence in item 2 — total cost of ownership is what carries the weight. This one leaves nothing you can act on in purchasing or product decisions today, and we log it as technical tracking. ⚠️ It is a design proposal at the paper stage, not a production yield, with an entire process qualification in between.

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On-chip high-speed memory shrinks 25% in area and writes 42% faster.

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The new flagship's enterprise edition went live with its first published prices, and its own account of the mechanism doubles as an audit cost.

OpenAI says its first in-house inference chip delivers 1.5 to 1.9 times the throughput per watt of "the commercial systems tested" — and does not say which systems those were.

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