Product & chips · Sep 2, 2026

Stacking transistors on top of each other finally has a yield number: 45% to 85%.

Chips & semiconductors · This week (published September 1)

From the Sep 2, 2026 daily brief

imec, in Belgium, is the shared advanced-process R&D center for the industry. The major foundries and equipment makers are all partners, and its roadmap tends to be read as the sector's common schedule. Its September 1 technical report covers CFET: stacking p-type and n-type transistors vertically so standard cell height falls from today's 5.5 tracks to 3. What is new today is that the numbers are no longer only about getting smaller. A new backside contact scheme raises bottom-device drive current five-fold, and surviving yield rises from 45% to 85% (Semiconductor Engineering, 09-01). Yield is the criterion that matters here: 45% to 85% is the first public manufacturability reading this path has produced. But it measures surviving yield on a single integration module, not the yield of a finished chip, and the two are not interchangeable. ⚠️ This is a research institute's pilot line, not a production commitment from any foundry. The reading to watch next is which foundry writes a CFET yield into a production announcement of its own.

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Stacking transistors on top of each other finally has a yield number: 45% to 85%.

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More in this section

Customers of chip-design tool vendors have started capping tokens engineer by engineer — and a year ago nobody cared what that line cost.

The new flagship's enterprise edition went live with its first published prices, and its own account of the mechanism doubles as an audit cost.

OpenAI says its first in-house inference chip delivers 1.5 to 1.9 times the throughput per watt of "the commercial systems tested" — and does not say which systems those were.

Meta launched a personal AI agent called Muse, and the part worth recording is not what it does but that a payment network has written terms for a non-human buyer for the first time.