AI news Sep 2, 2026

This week · published September 1

Stacking transistors on top of each other finally has a yield number: 45% to 85%.

imec, in Belgium, is the shared advanced-process R&D center for the industry. The major foundries and equipment makers are all partners, and its roadmap tends to be read as the sector's common schedule. Its September 1 technical report covers CFET: stacking p-type and n-type transistors vertically so standard cell height falls from today's 5.5 tracks to 3. What is new today is that the numbers are no longer only about getting smaller. A new backside contact scheme raises bottom-device drive current five-fold, and surviving yield rises from 45% to 85% (Semiconductor Engineering, 09-01). Yield is the criterion that matters here: 45% to 85% is the first public manufacturability reading this path has produced. But it measures surviving yield on a single integration module, not the yield of a finished chip, and the two are not interchangeable. ⚠️ This is a research institute's pilot line, not a production commitment from any foundry. The reading to watch next is which foundry writes a CFET yield into a production announcement of its own.