This week · preprint, arXiv 2610.39570

Itoh says an FPGA agent ran a test 9.6 times faster

Leo Itoh and Junichiro Kadomoto self-report that an agent testing the same CPU design on an FPGA finished 8,000 CoreMark iterations, build time included, 9.6 times faster than single-threaded RTL software simulation. Chip design teams and design-software vendors have to decide whether to rebuild the evaluation step first, so agents get fast feedback. The result is self-reported and comes from one human-supervised single-core design. The paper, submitted to ISCAS 2027, goes from a single-cycle RV32I core to a three-issue out-of-order RV32IM core, running on an Artix-7 FPGA at 130 MHz and scoring 5.61 CoreMark/MHz. The comparison is not production-grade parallel simulation (arXiv 2610.39570). How we checked →

Concept illustration of an open book whose spread has a black band of white capital lettering across the top and two rows below, each starting on the left page with the same person in a dark turtleneck seated at a desk, hand to chin, facing a laptop whose screen shows a speech bubble and a panel. In the upper row, under a black label reading SIMULATION, a black square plate with a chip outline sits near the left end of a long double-line track that crosses both pages to a stop at the far right; in the lower row, a cable runs from the laptop to a red circuit board under a black label reading FPGA, and a double-line track runs from the board across both pages to a matching black plate beside the stop at the far right.

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This item ran in the brief of Nov 1, 2026, alongside 7 other items. How we checked it, the quote checks and what was still missing that day are on that issue's How we checked page.

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SecondSource (2026). "Itoh says an FPGA agent ran a test 9.6 times faster." https://secondsource.io/en/research/2026-11-01-2/. Accessed access date.